Have the Glimpse of the CTS Course
· Section 1 - INTRODUCTION
Lecture 1: Introduction to Clock Tree Synthesis
· Section 2 - Clock Tree Quality Check Parameters
Lecture 2: Skew and Pulse Width Check
Lecture 3: Duty Cycle and Latency Check
Lecture 4: Latency and Power Check
Lecture 5: Power Check Continued
Lecture 6: Power and Crosstalk Quality Check
Lecture 7: Delta Delay Quality Check
Lecture 8: Glitch Quality Check
· Section 3 - H - Tree
Lecture 9: H-Tree Algorithm and Skew Check
Lecture 10: H-Tree Pulse Width and Duty Cycle Check
Lecture 11: H-Tree Latency and Power Check
· Section 4 - Clock Tree Modelling and Observations
Lecture 12: Clock Tree Modelling
Lecture 13: Clock Tree Building
Lecture 14: Clock Tree Buffering
Lecture 15: Clock Tree Observations
· Section 5 - Buffered H - Tree
Lecture 16: H-Tree Buffering Observations
Lecture 17: H-Tree Skew Check
Lecture 18: H-Tree Pulse Width Check and Issues with Regular
Buffers
Lecture 19: CMOS Inverter PMOS/NMOS Switching Resistance
Difference
Lecture 20: CMOS Inverter PMOS/NMOS Matching Switching
Resistance Solution
Lecture 21: H-Tree with Clock Buffers and Pulse Width Check
Lecture 22: H-Tree Duty Cycle, Latency and Power Checks
Lecture 23: Dynamic Power and Short Circuit Power
Lecture 24: Leakage Power
· Section 6 - Clock Tree Optimization Checklist
Lecture 25: Optimization Checklist
Lecture 26: Short Circuit Current Reduction Technique
Lecture 27: Leakage Current Reduction Technique
Lecture 28: Clock Tree Optimized
Lecture 29: Optimized Clock Tree Power and Latency Check
· Section 7 - Uneven Spread of Clock Endpoints
Lecture 30: Clock Tree for uneven Spread of Clock End Points
Lecture 31: Logical to Physical Connections
Lecture 33: Advanced H-Tree for Million Flop Clock Endpoints
with uneven Spread
· Section 8 - Power Aware Clock Tree Synthesis
Lecture 34: Introduction to Clock Gating cells
Lecture 35: Introduction to Delay Tables
Lecture 36: Delay Table Usage – I
Lecture 37: Delay Table Usage – II
Lecture 38: Clock Gating Technique using AND Gate and Skew
Issue
Lecture 39: Solution to Skew Issue
Lecture 40: Clock Gating Technique using both AND and OR
gate
Lecture 41: Clock Gating Technique using Universal NAND Gate
Lecture 42: Clock Gating Technique on Real Chip and its
impact on Power
· Section 9 - Static Timing Analysis
Lecture 43: Setup Timing Analysis with Real Clocks
Lecture 44: Introduction to Data Arrival Time, Data Required
Time and Slack
Lecture 45: Impact of Unbalanced Skew on Setup Time
Lecture 46: Hold Timing Analysis with Real Clocks
Lecture 47: Impact of Unbalanced Skew on Hold Time
· Section 10 - Summary
Lecture 48: Topics Learned and More To Come !!
