“When the best design work, great ideas is born”
Empowering Semiconductor through Online Learning
VSD pioneered the art of connecting the correct resources to the community to bring the revolution in VLSI Design process. Over last decade we have done enormous work in open source semiconductor domain via developing training content and enabling students to design silicon grade IP/SoC and also taken till tapeout cycle via Google/Efabless open shuttle program.
Master semiconductor design with hands-on courses. Build a strong foundation in digital logic, RTL, physical design, and verification for VLSI success.
This course will cover end-to-end description from basic Device Physics to Chip Design.
This course will give an eagle’s eye to every timing check that is being performed in current industries for sign-off.
Right time to move from “chip designing” to “chip planning”
VSD – Intelligent Assessment Technology (VSD-IAT) is expertly built training platform and is suited for designer requirement to offer high-intensity, lab-based RTL2GDS VLSI tapeout workshops tailored for freshers and mid-level professionals. These workshops start with basic concepts and gradually build complexity and highlight is the emphasis on using a consistent technology node, addressing common industry confusion.
Completed a comprehensive program on RISC-V on FPGA and OpenFPGA, covering design and architecture, tools for analysis and simulation, and implementing RISC-V cores on FPGA, supported by the Open-Source FPGA Foundation and industry experts. Gratitude expressed to mentors, contributors, and fellow participants, highlighting the program's goal to democratize hardware design
"The Chip Design for High School Program surpassed my expectations, offering an engaging and beneficial learning experience. The course content and teaching methods, combined with interesting lab sessions, made the program highly impactful. However, pacing the session uploads to three per week would improve the overall experience."
Successfully completed a 10-week research internship at VLSI System Design, focusing on designing a 4-Bit Asynchronous Up Counter in the Physical Design domain using open-source tools like Ngspice, Xschem, and OpenROAD. Utilized the FOSS 130 nm PDK from Google and SkyWater Technology Foundry.
Published on National Television DD News
RISC-V and VLSI Educational Board
VSD is conducting RISC-V Roadshow across India to create awareness about RISC-V and its potential to develop skilled manpower for India’s growing chip design ecosystem. This program will introduce students to foundational chip design concepts and explore exciting career opportunities in this sector.
Participants will gain insights into various aspects of electronic design, from RTL coding to physical implementation, and learn how RISC-V connects embedded systems, firmware, and hardware. The roadshow will highlight the importance of a multidisciplinary approach in driving innovation and shaping careers in the rapidly evolving semiconductor industry.
VSD is conducting RISC-V Roadshow across India to create awareness about RISC-V and its potential to develop skilled manpower for India’s growing chip design ecosystem. This program will introduce students to foundational chip design concepts and explore exciting career opportunities in this sector.
Participants will gain insights into various aspects of electronic design, from RTL coding to physical implementation, and learn how RISC-V connects embedded systems, firmware, and hardware. The roadshow will highlight the importance of a multidisciplinary approach in driving innovation and shaping careers in the rapidly evolving semiconductor industry.
VSD is working towards creating innovative talent pool who are ready to develop design and products for the new tech world. VSD believes in “Learning by doing principle” , and always prepare the student to apply the knowledge learned in the workshops, webinars and courses.
Exploring RISC-V ISA and its application in product-based environments
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SoC design planning using the revolutionary Google-SkyWater 130nm process node within the OpenLANE flow
Program by SFAL, Synopsys, and VSD