we are close… just wait ‘n’ watch!!
Hello Wondering…what are we closing on……!! So what if, I show you the below image which represents synthesized version some complex design (say, microprocessor)…you must […]
Monthly Archives: December 2016
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wondered how simply can layout be drawn from scratch ?
hello And that’s what I aim in my new course (yet to be released) Let me try to give you a basic snapshot of what […]
Let’s do some MAGIC!
Hello So can you identify what do the below images represent? One is, of-course, the SPICE netlist of CMOS inverter, and the other one is […]
Generated clock & master clock.. Let’s make it simple!! – Part 3
Hello So now that you get the point of generated clocks in previous Part 1 and Part 2 of this post, now let’s conclude this […]
Generated clock & master clock.. Let’s make it simple – Part 2
hello Based on the responses of previous post of Generated clock & master clock … Let’s make it simple!! – Part 1, I am very […]
Generated clock & master clock.. Let’s make it simple!! – Part 1
Hello I get this one occasionally … not particularly about the concept, but about the ways we can create a generated clock definition. Too many […]
Yes…I have money to build better chips!!!
Hello You guessed it right. I am referring to ‘fabless’ model of semiconductor business… Here I am referring to one of my post, which had […]
Some real good news for designers registered in my courses!!
hello I have been traveling last few days to Silicon Valley, San Jose US and would love to say, I have some real good news […]
My biggest challenge – Do I have money to build better chips?
Hello Of course …. The biggest cost that I am mentioning about is the fab cost and that’s my biggest challenge to build better chips. […]
Jitter analysis using eye diagram – Part 1
Hello For those who have been in sync with my course on Static timing analysis, will already know this topic very well. For those who […]
