Signal integrity (SI-glitch) – Part 3
Hello Hope you had a great weekend! I didn’t had one, as was busy preparing high quality videos on Circuit design and SPICE simulations, which will be […]
Monthly Archives: December 2016
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Signal integrity (SI-glitch) – Part 2
Hello First of all, I would like to ‘Thank You’ all for the messages/doubts that you have sent me over linkedin, vsd@vlsisystemdesign.com, facebook, etc. Really overwhelmed by the […]
Signal integrity (SI-glitch) – Part 1
Hello Let me start this with a 30 sec video Well …. That’s glitch … Plain and simple !!! 🙂 Ahhh…. It’s a pain … right […]
Common clock path pessimism removal (CPPR) – Part 4
Hello And you thought we are done with CPPR… No … not yet … We haven’t done the “Hold” analysis yet. Its simple, but its […]
Common clock path pessimism removal (CPPR) – Part 3
Hello It’s been 5 days since my last post (and that was intentional). I wanted to go slow on this topic, as this is an […]
Common clock path pessimism removal (CPPR) – Part 2
Hello Hope everyone had a good weekend :)! And the reason for this post is to help friends and people in my circle to crack […]
Common clock path pessimism removal (CPPR) – Part 1
Hello Let me quote “Winston S Churchill”, who said “A pessimist sees the difficulty in every opportunity; an optimist sees the opportunity in every difficulty.” […]
On-Chip Variation (OCV) – Part 4
Hello And, finally, we have a video on what we posted on this topic. Below is the snippet of the same. Full video can be […]
On-Chip Variation (OCV) – Part 3
Hello, The below image models “low-to-high waveform condition” at input of CMOS inverter, in terms of resistances and capacitance. So, overall, its the RC time […]
On-Chip Variation (OCV) – Part 2
Hello Today, I was a guest speaker at one of the biggest Technical Conference held in Bangalore, and luckily I met few people who had […]
