We thank Prof. V Kamakoti, IIT Madras for delivering Honorary Lectures in this workshop

Overview :

Verilog Hardware Description Language or Verilog-HDL has been widely used to model hardware since many years. From a specification to its hardware description, each phase of writing HDL code brings it’s own challenges and surprises. “So what exactly are these challenges?” “How can I describe a 32/64-bit ALU used in processors?” “Can I describe finite state machine is the most easiest way?” "Can I model PMOS/NMOS in verilog using primitives and simulate?" "Are MOS primitives synthesizable?"- If you have these questions and if you are eager to delve into the world of "Digital System Design and Modelling using Verilog". Wait no more!

This workshop is an OPPORTUNITY for all students across the globe, including VSD students, to learn from a Professor who has made our country India proud by releasing first ever Made In India RISC-V based processor Shakti. Don't miss this 1-day workshop on Digital System Design and modelling using Verilog. All the best

1-Day workshop with cloud based verilog labs

1. Basics of transistors and logic gates (1hour)
   1. CMOS Transistor theory (PMOS/NMOS/MOS Layers)
   2. Tx gates, inverter,
   3. Logic switches (NAND/NOR gates)
   4. Simulation using MOS primitives and iverilog simulator

2. Gate-level design and modelling (1hour 30min)
   1. Basic pos-level latch using CMOS Transistors
   2. Simulation of pos-level latch with blocks built using MOS primitives
   3. Structural representation of circuit and systems (eg. 32/64-bit adder)
   4. Parameterized simulation strategy of 32/64-bit adder

3. Sequential Circuit design (1hour 30min)
   1. Design representation (block diagram, state diagram, timing diagram, circuit diagram, verilog)
   2. State machine lab to count even and odd number of zero’s and one’s for a system
      Simulation hick-ups in above state-machine and need for hand-shaking protocols (request-ack, ready-valid signals)

NOTE - At the end of workshop, a very well-structured GitHub link for all above labs will be shared with all participants to practice after the workshop

Refund Policy:

1. Last date to apply for refund is 7 December 2020.
2. Students absent during Workshop NOT eligible for Refund.

1. iVerilog

1. Virtual Coach platform with expert instructor guidance
2. Cloud-based dedicated Virtual Machine to perform Design labs
3. Intelligent Assessment Technology (IAT) and Project allocation
4. 24 hours Lab access for 5 days and Instructor assistance on demand
5. Simulate verilog code using open source Verilog simulator

We thank Prof. V Kamakoti, IIT Madras for delivering Honorary Lectures in this workshop

Instructor Profile:

Prof.V. Kamakoti,  received the M.S. degree and the Ph.D. degree in Computer Science and Engineering from IIT Madras, Chennai, India.,He is currently a Professor with the Department of Computer Science and Engineering and Associate Dean at ICSR,IIT Madras. He has more than 25 years of experience in computer systems development and specializes in the area of computer architecture, CAD for VLSI, and high performance computing. Dr. Kamakoti took SHAKTI processor initiative which aim to break the barrier between Academia and Industry by providing open-source Processor and SoC designs. He has authored a number of research papers that have been published in various international journals and in the PROCEEDINGS of many scientific conferences.
Dr.Kamakoti received the DRDO Academic Excellence Award instituted by DRDO in recognition of the contribution from Academicians to various programs of DRDO. Recently, Dr.Kamakoti was awarded  Techno Visionary Award, which is a lifetime achievement award given to an Indian academician, who made significant contributions to the field of Electronics and Semiconductor through research and development.

Kunal Ghosh, co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., Kunal pioneers in the field of online open-source EDA (qflow & openroad)/open-source hardware (specially RISC-V) design and learning. Currently, Kunal owns around 32 high-quality VLSI online courses in and around open-source EDA/hardware, which is being consumed by around 28700+ students around 141 countries. Apart from trainings, Kunal has also worked with IIT Madras and IIT Guwahati on open-source activities and design projects. Currently, Kunal and his team are working on developing high quality open-source Analog/Digital IP’s which would be first one’s in the field of open-source hardware design. Prior to VSD, Kunal has worked with Qualcomm and Cadence, in field of SoC design. Kunal has done his Masters at IIT Bombay in field of VLSI & Nano-electronics, with specialisation in Sub-100nm Electron Beam LithographyOptimisation techniques