“Physical Verification using Skywater 130nm technology” Workshop intends to address various issues that come up during the design cycle as DRC/LVS violations. It aims to demonstrate the best approach to mitigate and rectify these violations. The course covers Physical Verification methodology using Magic,Netgen and OpenLane flow. It also explores the SKY130 PDK in detail, the knowledge of which is necessary to generate a robust design. This course starts with giving the basic idea of the design flow, PDK libraries and then takes a deep dive into the intricate concepts of Physical Verification with dedicated lecture and labs for each topic.

Day 1 Lectures: Introduction to SkyWater SKY130

1. Open_pdks
2. SkyWater PDK
3. Open tool setups
4. Libraries
5. 3rd-party packages
6. Projects
7. Understanding the Skywater PDK
8. Layers
9. Rules
10. Devices
11. Libraries
12. Digital standard cells
13. I/O cells

Day 1 Labs:

1. Open_pdks installation
2. Installing open_pdks and the SkyWater PDK
3. Project setup best practices
4. Setting up for layout with magic
5. Setting up for schematic capture with xschem
6. Setting up for LVS with netgen
7. Creating a SKY130 device layout in magic
8. Creating a simple schematic in xschem
9. Exporting a schematic to layout
10. Simulating the netlist

Day 2 Lectures: Introduction to DRC and LVS

1. Understanding GDS format
2. Streaming format
3. Layer:Purpose pairs
4. Hierarchy
5. Some tools/scripts for manipulating GDS
6. Understanding extraction and SPICE formats
7. Running extraction
8. ngspice
9. Extraction styles and options
10. ext2spice options
11. Extraction for LVS
12. Parasitic extraction
13. Full R-C extraction
14. GDS reading and writing in magic
15. Readonly option
16. Flatten options
17. Hierarchy & magic's database
18. Polygon subcells
19. Library option
20. Addendum option
21. Noduplicates option
22. Working with GDS styles
23. GDS special purpose styles
24. DRC rules in magic
25. Interactive DRC in magic
26. DRC vs. correct-by-design in magic
27. DRC rules hidden by hierarchy
28. DRC rules in the tech file
29. DRC verification layouts
30. Extraction rules in magic
31. Extraction styles
32. Device types
33. Hierarchical extraction
34. DRC errors uncovered by extraction
35. LVS setup for netgen
36. Setup options
37. Device description
38. SPICE vs. SPICE
39. SPICE vs. verilog
40. Black-boxing
41. Verification by XOR
42. ECO
43. XOR

Day 2 Labs:

1. Basic GDS:
2. Reading/writing GDS to/from magic
3. GDS compositing with magic
4. Vendor GDS
5. Reading unknown GDS (magic and klayout)
6. GDS read/write options
7. Basic extraction:
8. Extracting a SPICE netlist from magic
9. Extraction options
10. Parasitic extraction
11. Setup for DRC:
12. Running magic (on a prepared example)
13. Using DRC styles
14. Using alternative tech files
15. Running sign-off scripts
16. Viewing DRC in klayout
17. Setup for LVS
18. Netgen setup scripts
19. Running netgen (on a prepared example)
20. Setup for XOR
21. Creating an ECO (from a prepared example)
22. Running XOR

Day 3 Lectures: Front-end and back-end DRC

1. Back-end (metal layer) rules
2. Width
3. Spacing, Notch
4. Wide-spacing
5. Minimum Area
6. Via overlaps
7. Minimum hole
8. Slot rules
9. Via generation rules
10. Local Interconnect
11. Front-end rules
12. Transistor rules
13. Implants, ID layers, Boundary layers
14. Wells, Same-net rules
15. Deep N-well
16. High voltage rules
17. Resistors
18. Capacitors
19. Diodes
20. Fixed-layout devices
21. Miscellaneous rules
22. Off-grid errors
23. Restricted angles
24. Latchup rules
25. Antenna rules
26. Stress rules
27. Density rules
28. Why density rules?
29. Layer density requirements
30. Fill generation algorithm
31. Fill blocking
32. When automation fails
33. Recommended rules
34. Double vias
35. DRC in Magic:DRC styles
36. Dumping and viewing DRC results
37. Fixing DRC errors

Day 3 Labs:

1. Running Magic's interactive DRC
2. Running antenna checks
3. Running Magic's batch DRC
4. Running the fill generation script
5. Running the density checker script
6. Checks with alternative tech files
7. Catching violations by extraction

Day 4 Lectures: Understanding PNR and physical verification

1. OpenLANE/OpenROAD automation 
2. Non – Interactive mode of OpenLANE Flow
3. Interactive mode of OpenLANE Flow
4. Techniques To Avoid Common DRC Errors
5. Techniques To Manually Fix Violations

Day 4 Labs:

1. PNR flow Using OpenLANE Demo

Day 5 Lectures: Running LVS

1. Generating netlists from schematic
2. Generating LVS netlists from layout
3. Differences between LVS netlists and simulation netlists
4. How to prepare netlists for both simulation and LVS
5. Verilog vs. layout
6. Running netgen
7. Pre-match analysis
8. Hierarchical checking and flattening
9. Property checking
10. Pin checking
11. Series/Parallel combining
12. Symmetry breaking
13. Interpreting results
14. Fixing errors

Day 5 Labs:

1. Creating a (simple) hierarchical circuit in schematic
2. Exporting a schematic to netlist
3. Importing a schematic netlist into layout
4. Exporting a circuit layout to netlist
5. Creating a (simple) hierarchical circuit in verilog
6. Running LVS
7. Interpreting LVS results
8. Fixing LVS errors

• Xschem – A schematic capture and netlisting tool.
• Ngspice – An open-source spice simulator for electronic circuits.
• Magic – A layout editor tool.
• Netgen – A tool used for LVS check.
• OpenLane Flow – It performs full ASIC implementation steps from RTL all the way down to GDSII.

1. Virtual Coach platform with expert instructor guidance
2. Cloud-based dedicated Virtual Machine to perform Design labs
3. Intelligent Assessment Technology (IAT) and Project allocation
4. 24 hours Lab access for 5 days and Instructor assistance on demand

Timothy Edwards​, Founder Opencircuitdesign.com and SVP at Efabless​.Analog VLSI designer and collecting and developing open-source EDA tools for over 27 years . Worked for the Johns Hopkins Applied Physics Lab, startups MultiGiG and Analog Devices​.Developed open-source EDA software tools such as Magic, Qflow, Netgen, and Xcircuit​

Teaching Assitant

Anmol Purty is a VLSI enthusiast, who completed his Masters degree in VLSI Systems Design from National Institute of Technology, Warangal. He has worked on several projects related to Digital design, Analog IP design, Layout design, Physical Verification and Novel Spintronics devices. He possesses a good understanding of the ASIC Design flow, CMOS technology and Digital electronics.

Refund Policy: If you are not able to join workshop, last date to apply for refund in 8 November 2022, 11:59 PM IST

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