VSD - Clock Tree Synthesis - Part 1
Overview
Clock Tree Networks are Pillars and Columns of a Chip. With these series of lectures, we have explored on-site concepts applied in VLSI industry. It is a One-Stop-Shop to understand industrial VLSI circuits.The videos will develop an analytical approach to tackle technical challenges while building Clock Tree.
- CTS Quality Checks (Skew, Power, Latency, etc.)
- H-Tree
- Quality Check of H-Tree
- Clock Tree Buffering
- Buffered H-Tree
- H-Tree with uneven spread of Flops
- Advanced H-Tree for Million Flops
- Power Aware CTS (clock gating)
- Static Timing Analysis with Clock Tree
Objectives
- Introduction to Clock Tree Synthesis
-
Clock Tree Quality Check Parameters
- Skew and Pulse Width Check
- Duty Cycle and Latency Check
- Latency and Power Check
- Power Check Continued
- Power and Crosstalk Quality Check
- Delta Delay Quality Check
- Glitch Quality Check
- H-Tree
- H-Tree Algorithm and Skew Check
- H-Tree Pulse Width and Duty Cycle Check
- H-Tree Latency and Power Check
- Clock Tree Modelling and Observations
- Clock Tree Modelling
- Clock Tree Building
- Clock Tree Buffering
- Clock Tree Observations
- Buffered H - Tree
- H-Tree Buffering Observations
- H-Tree Skew Check
- H-Tree Pulse Width Check and Issues with Regular Buffers
- CMOS Inverter PMOS/NMOS Switching Resistance Difference
- CMOS Inverter PMOS/NMOS Matching Switching Resistance Solution
- H-Tree with Clock Buffers and Pulse Width Check
- H-Tree Duty Cycle, Latency and Power Checks
- Dynamic Power and Short Circuit Power
- Leakage Power
- Conclusion and next topics!
- Interview Questions
- Skew
- Buffer Levels
- Latency
- Clock Gating
- Setup Slack
- Setup Slack - I
- Short Circuit Power
- Delay Table
- Leakage Current
- Total Chip Power
Audience Profile
- Individuals keen to learn about VLSI and Chip World
Prerequisites
- Individuals having Basic Knowledge of Electrical and Electronics
Tools Used
NA
Buy the Course:
Presentation of the video courses powered by Udemy for WordPress.