Never really found a chance to properly introduce myself and my background to all of you. So here it is…

My name is Kunal Ghosh and below is a brief detail about my work—

@IIT Bombay (2007 – 2010)

I received MTech Degree in Department of Electrical Engineering (EE) from Indian Institute of Technology (IIT) Bombay in 2010 and specialized in VLSI Design & Nanotechnology during my 3-year tenure at IIT Bombay, from 2007 – 2010.

During my period at IIT Bombay, I worked with Prof. Richard Pinto and Prof. Anil Kottantharayil on “Sub-100nm optimization using Electron Beam Lithography”, which intended to optimize RAITH-150TWO Electron Beam Lithography tool and the process conditions to attain minimum resolution, use the mix-and-match capabilities of the tool for sub-100nm MOSFET fabrication and generate mask plates for feature sizes above 500nm.

During the same tenure, I also worked with Prof. Madhav Desai, to characterize RTL, generated from C-to-RTL AHIR compiler, in terms of power, performance and area. This was done by passing RTL, generated from AHIR compiler, through standard ASIC tool chain like synthesis and place & route. The resulting netlist out of PNR was characterized using standard software.

I co-authored a paper on the same “A C-to-RTL Flow as an Energy Efficient Alternative to Embedded Processors in Digital Systems” submitted in the conference “13th Euromicro Conference on Digital System Design, Architectures, Methods and Tools, DSD 2010, 1-3 September 2010, Lille, France”

 @Qualcomm (2010 – 2013)

After post-graduating from IIT Bombay, I worked in Qualcomm for a brief period of 3 years till 2013. Qualcomm is multinational semiconductor company involved in wireless technology. I worked there as a Lead Physical design and STA engineer for complex modems and memory test-chips.

During my tenure at Qualcomm, I was directly involved in taping out 12 test-chips (you heard it right, 12 full chips), while leading the entire sign-off timing closure for full chip and blocks. My team (mostly involved contractors from services company) was highly motivated due the complex problem statement that I posed before them.

Test-chips are generally the first-ever kind-of chips that tapes out for a certain technology node, and me & my team were the first ones in Qualcomm, to get hands-on on any new IP released at certain technology node. This was my first job and I was lucky enough to work from 45nm (MOSFET) to 16nm (FinFET) technology during first 3 years of my career.

The kinds of test chips involved were

·       MSM (mobile station mode chips) – MSM chips are used for CDMA modulation/demodulation. It consists of DSP’s and microprocessors for running applications such as web-browsing, video conferencing, multimedia services, etc.

·       Memory test chips – Memory test chips are used to validate functionality of 28nm custom/compiler memory as well as characterize their timing, power and yield.

·       DDR-PHY test chips – DDR-PHY test chips are basically tested for high speed data transfer

 @Cadence (2013 – 2017)

In 2013, I switched to Cadence Design systems, a design automation software company, as Lead Sales Application engineer, supporting and benchmarking Cadence STA tool. I worked closely with Cadence customers on tool evaluation and flow development, while also training them on latest Cadence technologies.

In this entire tenure of 4 years, I was directly involved in supporting Cadence STA tool Tempus for 14 customers (you again heard it right, 14 customers). This was a period, where I experienced the pulse of Static Timing Analysis core engine and how it behaves when moved from 130nm MOSFET technology node to 16nm FinFET technology node.

This was also a period when I was involved in benchmarking and evaluating a new technology for “IR aware STA” and “Low power STA”, which needed timing analysis using complex power domains

While supporting customers, I have sensed STA engine behavior for design size up to 850 million instance count (you again heard it right, 850 million). The STA technology needed to handle these kinds of design size was entirely fresh, and I was lucky enough to have hands-on experience on such design

Other than above extremely cornered designs and evaluation, I have published below papers at CDNLive conference:

·       Concurrent + Distributed MMMC STA for ‘N’ views

·       Signoff Timing and Leakage Optimization On 18M Instance Count Design With 8000 Clocks and Replicated Modules Using Master Clone Methodology With EDI Cockpit

·       Placement-aware ECO Methodology – No Slacking on Slack

So, now here I am…An open book…

Let’s catch up in person in my first webinar, whose details are here

Till then…happy learning