MAGIC Layout FAQ’s – Extract to SPICE
“Research is to see what everybody else has seen, and to think what nobody else has thought” – Let’s prove this by end of this […]
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MAGIC Layout FAQ – Where are colors in VLSI layout coming from?
Hey There, This is rather a very curious query I had, when I was learning Magic VLSI Layout tool, and I am very sure, every […]
MAGIC Layout FAQ – psubstratecontact and nsubstratecontact
Hey There, Now that it’s clear, that we can tapeout using open-source EDA tools (referring to recent RavenSoC tapeout by Efabless Corp. Pvt. Ltd. using […]
Probable errors while installing ‘vsdflow’ and its solutions
Hey There, Last week, I consulted around 20 colleges to install ‘vsdflow’ on their Linux Ubuntu and CentOS machines. There were many successful installations and […]
‘vsdflow’ on CentOS is ready
to build the shell script for ‘vsdflow’ on CentOS, and finally I have the first cut ready. You just need to follow steps given in below link for CentOS, and all opensource EDA tools (PNR, STA, Layout, LVS) will be installed on your system. There are 2 testcases (picorv32 and spi_slave) inside the below link to test whether all tools have been installed or not. After running the shell script in below link, you need run the testcase
How about benchmarking Opensource openSTA against ——?
So, I took up two STA tools, OpenSTA from openroad project and “——-” from “——-“, to explain, to some extent, what “bench-marking” means to me. I would also encourage everyone reading this blog to come up with their definitions of “bench-marks” for other tools and we can model that. You can fill-up “——” with one of your favorite industry grade EDA tools. The concept of benchmark won’t change
The horrible std cell ever designed by me….
Power rail discontinuity – We would like to have continuous power rail.N- and P-diffusion discontinuity – We would like to have continuous diffusion. For my Physical design friends, remember, we add “FILLER” cells at the end of routing, and you always wondered why we are doing so.Small substrate contacts – Except for inverter, all substrate contacts are single width, which will create high resistance path for current, thus increasing “Clk-to-Q” delay.Hanging metal1 – If you see for the NAND gate outputs, there is lot of hanging metal1.
Are you ready for Embedded-UVM webinar?
Hey There, Of-course there is a requirement for open-source verification, but that’s not the only thing we want to cater to. There are other verification […]
I wanna talk to hardware…I need Embedded Software Engineer
Hey There, It’s time – We are looking to talk to our hardware, and we need you in Bangalore (2-3 or 4-6 yrs work ex) […]
Selective Non-Default Rules Based Clock Tree Synthesis using open-source EDA
Hey There – Think about it…!! Problem Statement – For hierarchical designs ~500k instance count, participants are expected to develop code which will modify existing […]
