Can you approve my floorplan?
Just to give you some background, picoSoC is an example SoC using PicoRV32, and PicoRV32 is a size-optimized RISC-V CPU which implements RV32IMC instruction set architecture.
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Machine learning contest: And the winner is….
Last week we conducted Machine Learning contest where participants were asked to modify loss function program to bring out best possible accuracy in terms of mean and sigma, by designing a new multinomial model. We have a winner and a special mention
RISC-V waterfall diagram and hazards
The above waterfall diagram is representing a sequence of instructions that are fetched from memory and how they progress to the various stages of pipeline. In the above diagram you got program counter (P), fetch (F), decode (D), register read (R), execute (E) and register write (W). We fetch one instruction at a time. Potentially, you can fetch multiple instructions at a time, which would be a super-scalar architecture.
Use this tool for PNR – Its FREE
If you learn this tool and use it to build your own applications, you might end up presenting a paper in our online conference happening soon called “VSDOpen” – The first ever online conference on opensource EDA.
Characterize Level-shifter – It can’t get simpler than this
Well, that’s was just a demo of the powerful efabless platform. Do you want to know more about this powerful yet simple platform? Do you want to build complete SoC using this platform? We did an entire webinar on this, and here’s the copy of it.
Let’s predict future…And built it…
let’s identify what has happened till date in field of EDA/CAD using Machine intelligence. The image below shows the flow diagram for designing a chip. This is what has happened (or happening) in EDA using machine intelligence.
Listen from CEO/architect himself on Machine learning
This webinar will talk about how do you do that using Machine Learning and Deep Learning techniques. Participants for this webinar range from students to some of service company India head and Program managers. So we will cover from basics to advanced + labs on cloud.
Machine Intelligence webinar overview
Webinar presents a hands-on approach with session on GPUs, solving design automation problems with modern machine intelligence techniques by including step-by-step development of commercial grade applications including resistance estimation, capacitance estimation, cell classification and others using dataset extracted from designs at 20nm.
The beauty of slack-based timing ECO
A timing ECO should be power, performance and area aware and that was the crux of this webinar, where we discussed several strategies about how to do effective ECO as an expert .Slack based ECO is a beautiful strategy which helps you to achieve your timing target, while helping you to reduce on power and area
From VLSI to System Design (SoC) – The choice of SPI
SPI model is a master/slave model. There’s some SPI master which determines who gets to transmit and who gets to receive. The output from SPI master is called MOSI (Master Out Slave In). If you have 2 slaves, slave 1 and slave 2, as shown below, MOSI goes to all the slaves .Then you have another line MISO (Master In Slave Out). All the wires are connected, as shown in below image. Then you have a master only function called SCLK, which goes to all the slaves. Now also, there must be a slave select (SS) for S1 and a slave select for S2.
