Regular buffer v/s Clock buffer – Part 2
Hello I feel lucky and blessed, after my last post on “Regular buffer v/s Clock buffer – Part 1“, as I received couple of emails, […]
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Regular buffer v/s Clock buffer – Part 1
Hello, Everyone, who’s been a part of physical design or STA, must have definitely gone through this. When I thought about it, like 5 years […]
Clk-to-q delay, library setup and hold time – Part 2
Hello, This is in continuation to the previous post, where I explained about transistor level implementation of negative and positive latch. In this post, I […]
Clk-to-q delay, library setup and hold time – Part 1
Hello, I have been receiving multiple queries on what is clk-to-q delay, how’s it different from library setup time and library hold time, etc. I […]
SPEF Format – Part 3
Hello, I realized last night, that I was celebrating my work anniversary. Thanks Linkedin for reminding me that :). And, thought, let’s celebrate this one […]
Standard Parasitic Exchange Format (SPEF)-Part 2
Hello, Hope you liked my previous post on “SPEF Format”, and, there had been 4 days since my last post, so I believe the previous […]
Standard Parasitic Exchange Format (SPEF) Format – Part 1
Hello, So, this has been due for long time. May be because of tight tape out deadlines, this very important piece of Physical Design flow […]
Maze Routing – Lee’s Algorithm
Lee’s Algorithm guarantees there is exists a valid path and it’s the shortest path.
But, this algorithm is too time and memory consuming, To overcome, these short-comings, there are other more advanced algorithms like Line search Algorithm, Steiner Algorithms, etc.
