A keynote from Rick O’ Connor, executive director, RISC-V foundation, and we remember this to core of our heart, because of the below statement he made – “RISC-v is present in 27 countries and can be used by 57 % of population of World soon” That’s the spread of open-source ISA
Since then, we have promoted courses using a lot of open-source EDA tools like Opentimer for STA, qflow for Physical design, TL-verilog for pipelining, Yosys for Synthesis, Proton for EDA and many more. Not only that, we have organized an online conference (as you might be aware) and here’s the link with details:
https://www.vlsisystemdesign.com/vsdopen2018-2/
how the IEEE754 floating point standard designed the way it is. Every great design begins with an even better story. We all must have read blogs and watched videos about how to convert a decimal floating-point number to its binary form. We must have seen standard formulas of converting an IEEE754 standard floating-point number to its decimal form.
So glad and happy to let you know that we will be presenting in RISC-V workshop at IIT Madras, India, on July 19, 2018 at 2pm (organized by RISC-V foundation), and topic is something which we have mastered in last 7 years – its about a survey of E31 RISC-V core floorplan and its impact on power, performance and area.
That’s exactly what happened in DAC2018 at Moscone Center, San Francisco. I was invited for a talk in DAC summer school, on my work “vsdflow” which is also one of the main topics of discussion in my “TCL programming” course on Udemy. I would say, the entire DAC was a journey of events, exchange of ideas between brightest minds of the world.
Symposium VI – Standard cell layout/characterization, ECSM puts its number in the same arc as NLDM. The numbers you see in above image, below the cell_rise, cell_fall, rise_transition is all NLDM information. Under rise_transition, you will have ecsm_waveform and ecsm_capacitance. Now this is only one waveform, because we gave it only one load and one slope, just like we have one value under “rise_transition”. If we had 3×3 under rise_transition, then you would have had ecsm_waveform(“0”), ecsm_waveform(“1”), till ecsm_waveform(“8”), essentially 9 waveforms. And same thing with capacitance
A new company marked its presence in market amidst Intel, Purdue university, and other top industries in DAC 2018 (see below image). It took exactly […]
This blog is regarding abstract submission for VSDOpen2018, which is the first online conference in VLSI, that covers all aspects of semiconductor technology with prime focus to build SoC using RISC-V CPU by illustrating exciting ways using (only) opensource EDA tools.
DRC is something which (most likely) is supposed to fail in first instance. Let’s see what you do to fix them. In below eg. drc count is 25. Qrouter (an open-source router, which will be discussed in detail in webinar) is really good with some standard cell sets like the one which comes distributed with qflow, like OSU018, they are really nice one’s to work with. All the ports have nice squares, they don’t have these inside ‘L’ corners as shown below.
Do you want to find your answers too? Enroll in the upcoming webinar on “Distributed timing analysis” with Tsung-Wei, do labs on your own, understand the framework and I can guarantee you would be a better STA engineer or Lead than you were before 26th May.
Welcome to Ethical RISC-V IoT Workshop
The “Ethical RISC-V IoT Workshop” at IIIT Bangalore, organized in collaboration with VSD, is a structured, educational competition aimed at exploring real-world challenges in IoT and embedded systems. Participants progress through three stages: building an application, injecting and managing faults, and enhancing application security. The event spans from May 9 to June 15, 2024, culminating in a showcase of top innovations and an award ceremony. This hands-on hackathon emphasizes learning, testing, and securing applications in a collaborative and competitive environment.
Welcome to the World’s only online conference in Semiconductor Industry VSDOpen Conference. With enormous support and global presence of audience from different segments of industrial lobby and academia made a highly successful event. Evolution is change in the genetic makeup of a population over time, online conference is one kind evaluation everyone adapt soon.
VSD offers online course in complete spectrum of vlsi backend flow from RTL design, synthesis and Verification, SoC planning and design, Sign-off analysis, IP Design, CAD/EDA automation and basic UNIX/IT, Introduction to latest technology – RISC-V, Machine intelligence in EDA/CAD, VLSI Interview FAQ’s.
Current Reach – As of 2021, VSD and its partners have released 41 online VLSI courses and was successfully able to teach ~35900 Unique students around 151 countries in 47 different languages, through its unique info-graphical and technology mediated learning methods.
