Symposium V – Machine Intelligence in EDA/CAD applications

Symposium V – Machine Intelligence in EDA/CAD applications- Let’s investigate a simple Wire Resistance Estimate (WiRE) model
This is common design automation problem which is used for estimating timing and power characteristics for analysis and implementation for many steps in ASIC flow. We will restrict our scope to physical implementation only, where known quantity is “length” of wire and resistance is predicted.

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Symposium I – Front-end open-source EDA tool flows for IC design and verification

Question – Who doesn’t want a 3.5X improvement in their code size? I guess everyone wants efficient and effective improvement. Now these are just few tips to have the easy implementation of pipe-line. You are free to implement your ideas in TL-verilog, compile, simulate and see the improvements on your own. For few more tips, you might want to check out below course on “VSD – Pipelining RISC-
V with TL-verilog”

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Distributed timing analysis webinar

There are multiple places, we can introduce distributed computing to timing and major motivation is to speed up the timing closure. We have to analyze timing under different range of conditions, typically quantified as modes (test mode, functional mode) and corner (PVT). The number of combinations (timing views) you have to run is typically increasing exponentially with lower nodes. That’s where you need to need to distribute timing analysis across different machines.

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The Perfect Launch – By Kunal and Rajeev

We launched industry grade PNR EDA tool ‘Proton’ on web in front of 100 people across 7 countries, which I think, by far, has been a perfect launch for any partial open-source EDA tool.The below link has the details of the launch:
https://www.udemy.com/vsd-physical-design-webinar-using-eda-tool-proton/

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Facts – About below open-source EDA tool

Why “integrated”? Because at lower nodes, you have to integrate other parts of the flow. Sign-off (you can see power and timing buttons below), clock tree synthesis (you can see synthesis button) must be integrated, so we have a fully integrated PnR flow that we built from day one.

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