Courses – VLSI System Design

Courses taught by VSD Instructor

VSD – Physical Design Flow

VLSI – Building a chip is like building a city!!

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VSD – Clock Tree Synthesis – Part 1

VLSI – Building a chip is like building a city!!

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VSD – Clock Tree Synthesis – Part 2

VLSI – Building a chip is like building a city!!

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VSD – SoC Design of the PicoRV32 RISCV micro-processor

VLSI – Building a chip is like building a city!!

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VSD Intern – Mixed Signal Physical Design Flow with Sky130

Mixed signal Physical Design labs using OpenLANE/Sky130

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VSD – Static Timing Analysis – I

VLSI – Essential timing checks

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VSD – Static Timing Analysis – II

VLSI – Analyse your chip timing for free

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VSD – Library characterization and modelling – Part 1

VLSI – The heart of STA, PNR, CTS and Crosstalk

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VSD – Static Timing Analysis (STA) Webinar

Characterize your design performance LIVE with me, just the way the industry works

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VSD – Signal Integrity

LSI – Real and practical steps to build chip with minimum Signal Integrity issues!!

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VSD – Timing ECO (engineering change order) webinar

Let's design better chips

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VSD – Distributed timing analysis within 100 lines of code

Distribute, divide and rule

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VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130

How to configure ope-source compiler OpenRAM for 130nm technology node

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VSD Intern – Analog Bandgap Reference design using Sky130

LIVE labs BGR Circuit design and layout using Sky130 PDKs

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VSD Intern – Analog Comparator Design using Sky130

Comparator Circuit design and layout using Sky130 foundry PDKs

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VSD Intern – DAC IP design using Sky130 PDKs – Part 1 (specifications design)

Overview of DAC Theory, Circuit and project flow

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VSD Intern – DAC IP Design using Sky130 PDKs – Part 2 (circuit design)

10-bit DAC full circuit design using Xschem and Sky130 PDKs

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VSD Intern – DAC IP design using Sky130 PDKs – Part 3 (layout design)

10-bit DAC full layout design using Magic and Sky130 PDKs

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VSD Intern – 10-bit DAC design using eSim and Sky130

10-bit DAC full layout design using Magic and Sky130 PDKs

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VSD – A complete guide to install open-source EDA tools

A step towards freedom in IC design!!

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VSD – A complete guide to install Openlane and Sky130nm PDK

Another step towards freedom in IC design!!

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VSD – TCL programming – From novice to expert – Part 1

The Expert In Anything Was Once A Beginner

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VSD – TCL programming – From novice to expert – Part 2

The Conclusion

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VSD – RISCV : Instruction Set Architecture (ISA) – Part 1a

Let's talk to computers

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VSD – RISCV : Instruction Set Architecture (ISA) – Part 1b

Computers are famous for being able to do complicated things starting from simple programs – Let's find out HOW?

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VSD – Making the Raven chip: How to design a RISC-V SoC

Building a chip is like building a city….

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VSD – Mixed-signal RISC-V based SoC on FPGA

FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP

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VSD – Pipelining RISC-V with Transaction-Level Verilog

Front end VLSI design can’t get easier than this

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VSD – Circuit Design & SPICE Simulations – Part 1

Learn how things got started in VLSI

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VSD – Circuit Design & SPICE Simulations – Part 2

Learn how things got started in VLSI

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VSD – Custom Layout

VLSI – This is where design meets fabrication

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VSD – RTL Synthesis Q&A Webinar

Here are the answers, you were looking for….

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VSD – Pipelining RISC-V with Transaction-Level Verilog

Front end VLSI design can’t get easier than this

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VSD – Mixed-signal RISC-V based SoC on FPGA

FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP

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VSD – Embedded-UVM

Opensource Verification and Emulation

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VLSI – Essential concepts and detailed interview guide

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40 Basic Questions to Prepare in Combinational Circuits

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50 Basic Questions to Prepare in Sequential Circuits

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VSD – Physical Design Flow

VLSI – Building a chip is like building a city!!

Know More

VSD – Clock Tree Synthesis – Part 1

VLSI – Building a chip is like building a city!!

Know More

VSD – Clock Tree Synthesis – Part 2

VLSI – Building a chip is like building a city!!

Know More

VSD – SoC Design of the PicoRV32 RISCV micro-processor

VLSI – Building a chip is like building a city!!

Know More

VSD Intern – Mixed Signal Physical Design Flow with Sky130

Mixed signal Physical Design labs using OpenLANE/Sky130

Know More

VSD – Static Timing Analysis – I

VLSI – Essential timing checks

Know More

VSD – Static Timing Analysis – II

VLSI – Analyse your chip timing for free

Know More

VSD – Library characterization and modelling – Part 1

VLSI – The heart of STA, PNR, CTS and Crosstalk

Know More

VSD – Static Timing Analysis (STA) Webinar

Characterize your design performance LIVE with me, just the way the industry works

Know More

VSD – Signal Integrity

LSI – Real and practical steps to build chip with minimum Signal Integrity issues!!

Know More

VSD – Timing ECO (engineering change order) webinar

Let's design better chips

Know More

VSD – Distributed timing analysis within 100 lines of code

Distribute, divide and rule

Know More

VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130

How to configure ope-source compiler OpenRAM for 130nm technology node

Know More

VSD Intern – Analog Bandgap Reference design using Sky130

LIVE labs BGR Circuit design and layout using Sky130 PDKs

Know More

VSD Intern – Analog Comparator Design using Sky130

Comparator Circuit design and layout using Sky130 foundry PDKs

Know More

VSD Intern – DAC IP design using Sky130 PDKs – Part 1 (specifications design)

Overview of DAC Theory, Circuit and project flow

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VSD Intern – DAC IP Design using Sky130 PDKs – Part 2 (circuit design)

10-bit DAC full circuit design using Xschem and Sky130 PDKs

Know More

VSD Intern – DAC IP design using Sky130 PDKs – Part 3 (layout design)

10-bit DAC full layout design using Magic and Sky130 PDKs

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VSD Intern – 10-bit DAC design using eSim and Sky130

10-bit DAC full layout design using Magic and Sky130 PDKs

Know More

VSD – A complete guide to install open-source EDA tools

A step towards freedom in IC design!!

Know More

VSD – A complete guide to install Openlane and Sky130nm PDK

Another step towards freedom in IC design!!

Know More

VSD – TCL programming – From novice to expert – Part 1

The Expert In Anything Was Once A Beginner

Know More

VSD – TCL programming – From novice to expert – Part 2

The Conclusion

Know More

VSD – RISCV : Instruction Set Architecture (ISA) – Part 1a

Let's talk to computers

Know More

VSD – RISCV : Instruction Set Architecture (ISA) – Part 1b

Computers are famous for being able to do complicated things starting from simple programs – Let's find out HOW?

Know More

VSD – Making the Raven chip: How to design a RISC-V SoC

Building a chip is like building a city….

Know More

VSD – Mixed-signal RISC-V based SoC on FPGA

FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP

Know More

VSD – Pipelining RISC-V with Transaction-Level Verilog

Front end VLSI design can’t get easier than this

Know More

VSD – Circuit Design & SPICE Simulations – Part 1

Learn how things got started in VLSI

Know More

VSD – Circuit Design & SPICE Simulations – Part 2

Learn how things got started in VLSI

Know More

VSD – Custom Layout

VLSI – This is where design meets fabrication

Know More

VSD – RTL Synthesis Q&A Webinar

Here are the answers, you were looking for….

Know More

VSD – Pipelining RISC-V with Transaction-Level Verilog

Front end VLSI design can’t get easier than this

Know More

VSD – Mixed-signal RISC-V based SoC on FPGA

FPGA flow for Mixed Signal SoC with RISC-V based core and PLL IP

Know More

VSD – Embedded-UVM

Opensource Verification and Emulation

Know More

VLSI – Essential concepts and detailed interview guide

Know More

40 Basic Questions to Prepare in Combinational Circuits

Know More

50 Basic Questions to Prepare in Sequential Circuits

Know More

SoC planning and Design

Sign-off analysis

Analog IP design using SKY130

CAD/EDA Automation and Basic UNIX/IT

RISC-V, Machine Intelligence in EDA/CAD

Circuit Design and Layout fundamentals

RTL design, Synthesis, FPGA and Verification

VLSI Interview related Course and blogs

SoC planning and Design

Sign-off analysis

Analog IP design using SKY130

CAD/EDA Automation and Basic UNIX/IT

RISC-V, Machine Intelligence in EDA/CAD

Circuit Design and Layout fundamentals

RTL design, Synthesis, FPGA and Verification

VLSI Interview related Course and blogs

"Join Chip Design for High School (Grade 6-12)"

Courses taught by VSD Instructor

VSD – Physical Design Flow

VSD – Clock Tree Synthesis – Part 1

VSD – Clock Tree Synthesis – Part 2

VSD – SoC Design of the PicoRV32 RISCV micro-processor

VSD Intern – Mixed Signal Physical Design Flow with Sky130

VSD – Static Timing Analysis – I

VSD – Static Timing Analysis – II

VSD – Library characterization and modelling – Part 1

VSD – Static Timing Analysis (STA) Webinar

VSD – Signal Integrity

VSD – Timing ECO (engineering change order) webinar

VSD – Distributed timing analysis within 100 lines of code

VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130﻿

VSD Intern – Analog Bandgap Reference design using Sky130

VSD Intern – Analog Comparator Design using Sky130

VSD Intern – DAC IP design using Sky130 PDKs – Part 1 (specifications design)

VSD Intern – DAC IP Design using Sky130 PDKs – Part 2 (circuit design)﻿

VSD Intern – DAC IP design using Sky130 PDKs – Part 3 (layout design)﻿

VSD Intern – 10-bit DAC design using eSim and Sky130

VSD – A complete guide to install open-source EDA tools

VSD – A complete guide to install Openlane and Sky130nm PDK

VSD – TCL programming – From novice to expert – Part 1

VSD – TCL programming – From novice to expert – Part 2

VSD – RISCV : Instruction Set Architecture (ISA) – Part 1a

VSD – RISCV : Instruction Set Architecture (ISA) – Part 1b

VSD – Making the Raven chip: How to design a RISC-V SoC

VSD – Mixed-signal RISC-V based SoC on FPGA

VSD – Pipelining RISC-V with Transaction-Level Verilog

VSD – Circuit Design & SPICE Simulations – Part 1

VSD – Circuit Design & SPICE Simulations – Part 2

VSD – Custom Layout

VSD – RTL Synthesis Q&A Webinar

VSD – Pipelining RISC-V with Transaction-Level Verilog

VSD – Mixed-signal RISC-V based SoC on FPGA

VSD – Embedded-UVM

VLSI – Essential concepts and detailed interview guide﻿

40 Basic Questions to Prepare in Combinational Circuits﻿

50 Basic Questions to Prepare in Sequential Circuits﻿

VSD – Physical Design Flow

VSD – Clock Tree Synthesis – Part 1

VSD – Clock Tree Synthesis – Part 2

VSD – SoC Design of the PicoRV32 RISCV micro-processor

VSD Intern – Mixed Signal Physical Design Flow with Sky130

VSD – Static Timing Analysis – I

VSD – Static Timing Analysis – II

VSD – Library characterization and modelling – Part 1

VSD – Static Timing Analysis (STA) Webinar

VSD – Signal Integrity

VSD – Timing ECO (engineering change order) webinar

VSD – Distributed timing analysis within 100 lines of code

VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130﻿

VSD Intern – Analog Bandgap Reference design using Sky130

VSD Intern – Analog Comparator Design using Sky130

VSD Intern – DAC IP design using Sky130 PDKs – Part 1 (specifications design)

VSD Intern – DAC IP Design using Sky130 PDKs – Part 2 (circuit design)﻿

VSD Intern – DAC IP design using Sky130 PDKs – Part 3 (layout design)﻿

VSD Intern – 10-bit DAC design using eSim and Sky130

VSD – A complete guide to install open-source EDA tools

VSD – A complete guide to install Openlane and Sky130nm PDK

VSD – TCL programming – From novice to expert – Part 1

VSD – TCL programming – From novice to expert – Part 2

VSD – RISCV : Instruction Set Architecture (ISA) – Part 1a

VSD – RISCV : Instruction Set Architecture (ISA) – Part 1b

VSD – Making the Raven chip: How to design a RISC-V SoC

VSD – Mixed-signal RISC-V based SoC on FPGA

VSD – Pipelining RISC-V with Transaction-Level Verilog

VSD – Circuit Design & SPICE Simulations – Part 1

VSD – Circuit Design & SPICE Simulations – Part 2

VSD – Custom Layout

VSD – RTL Synthesis Q&A Webinar

VSD – Pipelining RISC-V with Transaction-Level Verilog

VSD – Mixed-signal RISC-V based SoC on FPGA

VSD – Embedded-UVM

VLSI – Essential concepts and detailed interview guide﻿

40 Basic Questions to Prepare in Combinational Circuits﻿

50 Basic Questions to Prepare in Sequential Circuits﻿

VSD – Physical Design Flow

VSD – Clock Tree Synthesis – Part 1

VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130

VSD Intern – DAC IP Design using Sky130 PDKs – Part 2 (circuit design)

VSD Intern – DAC IP design using Sky130 PDKs – Part 3 (layout design)

VLSI – Essential concepts and detailed interview guide

40 Basic Questions to Prepare in Combinational Circuits

50 Basic Questions to Prepare in Sequential Circuits

VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130

VSD Intern – DAC IP Design using Sky130 PDKs – Part 2 (circuit design)

VSD Intern – DAC IP design using Sky130 PDKs – Part 3 (layout design)

VLSI – Essential concepts and detailed interview guide

40 Basic Questions to Prepare in Combinational Circuits

50 Basic Questions to Prepare in Sequential Circuits

VSD Intern – OpenRAM configuration for 4kB SRAM using Sky130

VSD Intern – DAC IP Design using Sky130 PDKs – Part 2 (circuit design)

VSD Intern – DAC IP design using Sky130 PDKs – Part 3 (layout design)

VLSI – Essential concepts and detailed interview guide

40 Basic Questions to Prepare in Combinational Circuits

50 Basic Questions to Prepare in Sequential Circuits

Date for Registration : 9th May - 22nd May, 2024
Hackathon Inauguration : 23rd May 2024