In this workshop, we broadly cover 5 modules. The first module focuses on taking a digital design through Xilinx Vivado and programming it on the FPGA. We also demonstrate area, timing analysis and post implementation simulation. In the second module we describe the OpenFPGA framework and demonstrate the VTR tool flow on two designs with an example architecture. Next, we repeat these tasks for a RISC-V based processor called RVMyth. We simulate RVMyth with a testbench through Vivado and program it on a Basys3 board. We then take it through the OpenFPGA framework through Skywater OpenSource FPGA (SOFA). We also demonstrate area, timing analysis and post implementation simulation for the processor core after taking it through SOFA. Lastly, we summarize the area and timing results obtained by the design from Basys3 and VTR.

Xilinx Vivado --> https://www.xilinx.com/support/download.html

OpenFPGA framework-->   https://openfpga.readthedocs.io/en/master/tutorials/getting_started/compile/

Verilog to routing (VTR) --> https://github.com/verilog-to-routing/vtr-verilog-to-routing

Skywater OpenSource FPGA (SOFA) --> https://github.com/lnis-uofu/SOFA

FPGA Board used:

Dr. Nanditha Rao is an Assistant Professor in the VLSI Systems group at IIIT Bangalore. She obtained her PhD in Electrical Engineering from IIT, Bombay in 2017. Her current research interests are in the area of processor architecture, RISC-V based designs, FPGA based designs, FPGA based acceleration of neural networks and radiation tolerant/hardened designs. Prior to joining for PhD, she worked as a Hardware design engineer (mainly Signal Integrity) at Intel Technologies, Bangalore for a period of 5+ years. At Intel, she was mainly responsible for signal integrity simulations of motherboard interconnects for high-speed differential interfaces such as pci-express, LVDS, DisplayPort, HDMI and so on. She interacted with customers in the Asia Pacific region on motherboard design guidelines and specialized in buffer modeling.

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Are there any prerequisites for the workshop?

Basic knowledge of digital design and electronics.

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The Registration fees is  $70, which includes 5 Day access to Cloud platform, Video lectures, and Lab Tutorials, 24 * 2 QnA platform where TA will solve all the queries immediately and 1 Hour LIVE Interactive Session everyday at 8 PM IST for 6 days. ( One day before workshop starts to give access labs and platform.)

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Yes. The workshop is conducted on VSD-IAT cloud platform, which allows you to login at your convenient time within 24hrs from start date in 12:00 AM IST time zone

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Can VLSI freshers join this workshop?

Yes, it will be very helpful for VLSI freshers as they can learn about the Open-source FPGA fabric, design and architecture , which will enable them to explore this field on their own and learn. So as long as you are looking forward to learning something new and making a bright career in the field of VLSI, you are welcome.The workshop is designed in such a way that, we start with the basics first and then move on to advanced concepts. Have a look at curriculum in above registration link.

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In one of our last workshop, we had students as young as 8th Grade. So as long as you are looking forward to learning something new and making a bright career in the field of FPGA, you are welcome. This workshop, though it's called advanced, is kept at a very very basic level, where we make sure basics are covered first. Look at curriculum in above registration link

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Is this workshop also for experienced VLSI engineers?

Yes, If you are an experienced VLSI professional and want to learn about the OpenFPGA Fabric design, you are welcome to join this workshop.

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You will be given lifetime access to all lab files after the workshop. Access to videos and VSD-IAT platform will terminate on last day of Workshop

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No. Labs will be done on VSD-IAT cloud platform. You will be given access to a Linux Terminal, which has all necessary tools installed. Post workshop, we will provide scripts to install all tools on your laptops so you can do all experiments on your laptop and revise