VSD-Hardware Design Program

Welcome to the fascinating universe of Hardware Design, where the pulse of every IC design cycle beats. Imagine transforming a bare RTL netlist into a masterpiece of engineering, the final tape-out. Each stage in the PnR process is a new chapter filled with unique challenges and revelations.

Overview

Do you find yourself asking, “What are these obstacles?” “How does this intricate process work?” “Could I actually create my own chip?” If these questions ignite your curiosity and you’re passionate about delving into the ASIC design flow, your adventure starts here!

We’re excited to introduce a game-changer: the Google-Sky Water collaboration has unveiled the first open source, manufacturable 130nm process design kit (pdk). This innovation transcends the boundaries of academic research and small-scale projects, propelling the open-source EDA world into a new dimension. Coupled with the inception of Openlane flow, a fully automated RTL2GDSII process, we’re closer than ever to realizing the dream of “an IC for everyone.”

Get ready for the ultimate program on SoC design planning using the revolutionary Google-SkyWater 130nm process node within the OpenLANE flow. This program is your gateway to:

  • Crafting and characterizing your own standard cell.
  • Gaining practical experience in the Physical Design domain.
  • Generating a complete GDSII from an RTL netlist.
  • Diving into and enriching the open-source EDA landscape.

Seize this unparalleled opportunity to transform your passion into expertise!

4 compelling reasons to join this program

  • Unprecedented Flexibility in Learning:

The program’s use of the VSD-IAT cloud platform enables unparalleled flexibility. Participants can access the course material and complete labs at any time within the specified program period. This feature caters to the diverse schedules of participants globally, making it ideal for anyone regardless of their time zone or daily commitments.

  • Comprehensive Support System

The round-the-clock availability of instructors and Teaching Assistants on Slack sets this program apart. Such constant support ensures that participants can receive immediate help, clarifications, or guidance, significantly enhancing the learning experience and reducing the likelihood of prolonged obstacles in their study.

  • Lifetime Access to Key Resources

Post-program, participants gain lifetime access to all lab files, a unique offering that allows for continued practice and mastery of skills long after the program has concluded. This ongoing access to resources is a significant advantage for long-term learning and skill retention.

  • Tailored to a Wide Range of Learners

The program is designed to be inclusive and beneficial for a broad audience – from second-year engineering students to seasoned professionals looking to share their expertise. This inclusive approach, combined with starting from the basics before advancing to more complex topics, ensures that the program is both accessible and challenging for participants at different levels of their educational or professional journey.

Open-Source Tools

Here’s a sneak peek at the powerful open-source tools you’ll be mastering, each a key player in the transformative journey of IC design:

  • Yosys – The Synthesis Powerhouse: Unleash your design’s potential with Yosys, a tool that transforms high-level, abstract descriptions into a detailed hardware blueprint. It’s where your ideas begin to take shape.
  • OpenLANE – The RTL2GDS Conductor: Journey through the RTL2GDS process with OpenLANE, your guide to turning raw RTL designs into GDSII files. It’s the path to turning concepts into reality.
  • NGSpice – The Characterization Maestro: Delve into the heart of characterization with NGSpice. Here, you’ll see how theoretical designs behave in the real world, an essential step for any aspiring IC designer.
  • Magic – The Layout and Floorplanning Wizard: Enter the realm of Magic for layout and Floorplanning. It’s where your designs gain structure and form, a crucial stage in bringing your chip to life.
  • OpenSTA – The Guardian of Timing Analysis: With OpenSTA, embark on a journey through the crucial stages of pre-layout and post-layout static timing analysis. Ensure your designs not only function but excel in timing precision.

Foundation of Innovation: Our Reference Design Base

(But you are free to choose a simpler design)

  • RISC-V based PicoRV32 SoC : At the core of our program is the PicoRV32, a RISC-V based SoC. It’s the canvas for your creativity, offering a real-world application of the skills and tools you’ll acquire.

Join us as we explore these incredible tools, each a gateway to mastering the art of IC design. This program isn’t just about learning; it’s about transforming knowledge into power, ideas into reality.

VSD Hardware Design Program Content

Week 1

Setting Up Environment and Introduction to RISC-V

Objective:

Get familiar with the environment, tools, and basic RISC-V workflow.

Tasks:

  1. Create a GitHub repository for storing all assignments and snapshots.
  2. Install the RISC-V toolchain using the VDI shared on WhatsApp.
  3. Follow the C-based Lab and RISC-V Lab videos. Replicate the steps on your machine.
  4. Upload snapshots of:
    • Compiled C code.
    • RISC-V Objdump output.

Deliverable:

GitHub repo with snapshots and documentation.

Week 2

SPIKE Simulation and Optimization Levels

Objective:

Understand the impact of optimization flags in RISC-V.

Tasks:

  1. Perform SPIKE simulation with -O1 and -Ofast flags.
  2. Upload the following to the GitHub repo:
    • Compiled C code.
    • RISC-V Objdump outputs for both flags.

Deliverable:

GitHub repo with simulation results and detailed observations.

Week 3

RISC-V Instruction Identification

Objective:

Decode and analyze RISC-V instructions.

Tasks:

  1. Identify instruction types (R, I, S, B, U, J) for given instructions.
  2. Write the exact 32-bit instruction code for each in the specified format.
  3. Upload all patterns to the GitHub repo.

Deliverable:

Documented 32-bit instruction patterns.

Week 4

Functional Simulation with Verilog

Objective:

Gain experience in Verilog functional simulation.

Tasks:

  1. Use the provided RISC-V core Verilog netlist and testbench.
  2. Run functional simulation and capture waveforms.
  3. Upload waveform snapshots and code to GitHub.

Deliverable:

  • GitHub repo with waveforms and simulation files.

Week 5

Building a 5-Stage Pipeline Processor

Objective:

Implement a pipelined RISC-V processor.

Tasks:

  1. Refer to detailed lab lectures on VSDIAT.
  2. Build a 5-stage pipelined processor.
  3. Append your initials to the clock signal name.
  4. Upload simulation files and waveform snapshots.

Deliverable:

GitHub repo with design files, documentation, and waveforms.

Week 6

BabySoC Integration and Functional Verification

Objective:

Integrate rvmyth with BabySoC and verify outputs.

Tasks:

  1. Install required tools (Icarus Verilog, GTKWave, Yosys, OpenSTA).
  2. Download BabySoC files and edit the top-level Verilog to integrate rvmyth.
  3. Simulate and capture waveforms for PLL, DAC, and 10-bit outputs.
  4. Ensure username and date are visible in the snapshots.

Deliverable:

GitHub repo with integrated design and waveform outputs.

Week 7

RISC-V Synthesis and Functional Comparison

Objective:

Perform synthesis and compare functional and synthesized outputs.

Tasks:

  1. Synthesize the RISC-V design.
  2. Compare functional and synthesized waveforms for the first 20 cycles.
  3. Capture and upload snapshots showing standard cells in GTKWave.

Deliverable:

GitHub repo with comparisons and synthesis snapshots.

Week 8

Timing Analysis and STA

Objective:

Perform Static Timing Analysis (STA) on RISC-V design.

Tasks:

  1. Set clock period, setup/hold uncertainties, and clock/data transitions.
  2. Run STA using OpenSTA for all timing corners.
  3. Upload snapshots of:
    • SDC file.
    • Setup and hold timing reports.
    • WNS/WHS table and graph.

Deliverable:

GitHub repo with detailed STA analysis and graphs.

Week 9

Advanced Physical Design Using OpenLane

Objective:

Understand advanced physical design workflows.

Tasks:

  1. Complete the “Advanced Physical Design using OpenLane” workshop.
  2. Document all labs and workflows, including:
    • Routed database.
    • Quality of Results (QoR).
    • Heatmap analysis.
  3. Upload detailed documentation to the GitHub repo.

Deliverable:

GitHub repo with detailed OpenLane design analysis and documentation.

Week 10

SoC Design Implementation Using OpenROAD

Objective:

Perform SoC design implementation using OpenROAD.

Tasks:

  1. Install OpenROAD flow scripts on your local machine.
  2. Study and document:
    • Basic OpenROAD flow setup.
    • Macro flow setup.
  3. Include Routed Database, QoR analysis, and Heatmap visualization for BabySoC.
  4. Ensure detailed documentation is included in the GitHub repo.

Deliverable:

GitHub repo with SoC implementation project files and analysis.

Final Submission

Ensure the GitHub repository is complete with:

  • Organized folders for each week’s tasks.
  • Detailed README files for every task.
  • Clear documentation and snapshots.
  • All waveforms and comparison graphs.

Curriculum

Program Week-wise Content Breakdown:

  • Week 1 : Foundations of VLSI Design
  • Introduction to Verilog RTL Design and Synthesis.
  • Timing Libraries (QTMs/ETMs), Hierarchical vs Flat Synthesis, Efficient Flop Coding Styles.
  • Combinational and Sequential Optimizations.
  • Week 2 : Synthesis and Optimization
  • Gate-Level Synthesis (GLS), Blocking vs Non-Blocking, Synthesis-Simulation Mismatch.
  • Optimization in Synthesis.
  • Week 3 : Simulation and Constraints
  • Pre-Synthesis and Post-Synthesis Functionality Simulation with PPA Calculation.
  • Basic SDC (Synopsys Design Constraints) Constraints.
  • Advanced SDC Constraints.
  • Week 4 : Advanced Design and Analysis
  • Constraint Development for Design.
  • Introduction to Static Timing Analysis (STA) and the Importance of MOSFETs in STA/EDA.
  • Week 5 : In-Depth CMOS Analysis
  • Basics of NMOS Drain Current (Id) vs Drain-to-Source Voltage (Vds).
  • Velocity Saturation and Basics of CMOS Inverter Voltage Transfer Characteristic (VTC).
  • CMOS Switching Threshold and Dynamic Simulations.
  • CMOS Noise Margin Robustness Evaluation.
  • CMOS Power Supply and Device Variation Robustness Evaluation.
  • Week 6 : Post-Synthesis Evaluation
  • Post Synthesis STA Checks for Design on Different Process Corners (ss, ff, tt).
  • Week 7 : EDA, PDK, and Floorplanning
  • Inception of EDA and PDK.
  • Understanding the Importance of Good Floorplan vs Bad Floorplan and Introduction to Library Cells.
  • Design and Characterization of a Library Cell Using a Layout Tool and Spice Simulator.
  • Pre-Layout Timing Analysis and Importance of Good Clock Tree.
  • Final Steps for RTL2GDS.
  • Week 8 : Finalizing the Design
  • Full RTL2GDS for Design.
  • Post Placement Pre CTS (Clock Tree Synthesis) STA Checks for Design on Different Corners and Comparison with Post-Synthesis.
  • Week 9 : Comprehensive STA Checks
  • Post CTS Pre-Layout STA Checks for Design on Different Corners and Comparison with Pre-CTS.
  • Week 10 : Final Evaluations
  • Post Layout STA Checks for Design on Different Corners and Comparison with Pre-Layout.

Join us for this transformative journey and turn your fascination into tangible skills in the ever-evolving world of IC design!

Delivery Mode

We’ve tailored every aspect of the program to ensure an effective and enjoyable learning journey:

Labs at Your Convenience

Practical Get hands-on experience with our easy-to-access labs, available through a virtual box image. We’ll provide clear, step-by-step instructions to help you set up and make the most of these labs, starting one day before the program kicks off.

Insightful Lectures on an Innovative Platform

Discover the intricacies of Physical Design with our comprehensive lectures, hosted on the VSD-IAT LMS platform. This intuitive platform not only gives you access to all necessary course materials but also allows you to explore the content at a pace that suits you.

Round-the-Clock Q&A Support

Have questions or need clarifications? Our team of instructors and Teaching Assistants (TAs) are available 24/7 on Slack during the 5-day program. We’re here to assist you whenever you need it, ensuring a smooth learning experience.

Daily Check-in Calls for Direct Interaction

Join us for a daily one-hour call, a perfect opportunity to address any immediate concerns, discuss challenges, and get direct guidance from our instructors and TAs. These calls are designed to keep you connected and supported throughout your learning journey.

Instructor Profile

Meet Your Guides to the World of VLSI Design


Kunal Ghosh Kunal Ghosh, the visionary co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., stands at the forefront of online open-source EDA and hardware design education, particularly in the realm of RISC-V.

With a portfolio of 50 top-tier VLSI online courses, Kunal has enriched the learning journey of over 90,000 students across 153 countries. His expertise extends beyond training; he’s actively involved in pioneering open-source projects and design collaborations with esteemed institutions like IIT Madras, IIT Bombay, IIT Guwahati and IIT Hyderabad.

His current focus is on crafting high-quality open-source Analog/Digital IPs, a groundbreaking endeavor in open-source hardware design. Kunal’s rich industry experience includes roles at Qualcomm and Cadence, specializing in SoC design. He holds a master’s degree from IIT Bombay, where he specialized in VLSI & Nano-electronics, with a focus on sub-100nm Electron Beam Lithography Optimization techniques.

FAQ

What’s the cost to register?

We’ve set a special discounted fee of $450 ($999). Our aim is to make Open-source EDA tools and PDKs accessible for various purposes such as college projects, PhD research, semester lectures, and keeping up with industry trends.

Can I participate according to my schedule?

Absolutely! The program is hosted on the VSD-IAT cloud platform, offering flexibility to log in at your convenience. The platform is accessible 24 hours a day during the ten weeks duration of the program.

I’m a second-year engineering student. Is this program suitable for me?

Definitely! We welcome learners of all ages and backgrounds. Our previous RISC-V program included students as young as those in 8th grade. This program, while advanced in title, starts with the basics to ensure a solid foundational understanding.

Can experienced system designers join to refresh their knowledge?

This program is primarily designed for newcomers to the field of VLSI. However, experienced professionals interested in sharing their expertise with students are more than welcome to join.

Will I have access to the program content after it ends?

Yes, you will receive lifetime access to all lab files. However, access to the videos and the VSD-IAT platform will end with the program.

Do I need to install any software for the labs?

No, all labs will be conducted on the VSD-IAT cloud platform using a Linux Terminal with all necessary tools pre-installed. Post-program, we will provide scripts for you to install these tools on your own computer for further practice and revision.

How are the labs distributed for this program?

Labs will be shared via a virtual box image. You’ll receive detailed instructions on accessing and using this image a day before the program starts.

What platform is used for the lectures?

Lectures will be delivered through the VSD-IAT LMS platform. This platform allows you to access course materials and interact with the content at your own pace.

Is there support available during the program?

Yes, our instructors and Teaching Assistants are available 24/7 on Slack throughout the 10 week program to answer questions, provide clarifications, and help.

Is there a specific time for addressing urgent issues?

Indeed, there’s a daily one-hour sync-up call during the program. This is a valuable time for discussing any immediate issues, challenges, and for receiving direct guidance from instructors and TAs.

Is the program flexible for asynchronous participation?

Yes, the program is hosted on a cloud-based platform, allowing you to access materials and complete tasks at your convenience, ensuring flexibility in your learning schedule.

Terms & Conditions

If you are not available to attend the program, Raise refund request before the last day of registration date in Indian Standard Time zone for the training/workshop/design program.

Last date to raise refund request– (2 Nov 2024 11:59 PM IST)

All refunds will be processed within 10 working days after the refund request is approved by VSD.

Please read Terms and Condition Policy : https://www.vlsisystemdesign.com/terms-and-conditions/

About VSD

VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.

Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.

At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.

We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.

Program Date

36,580
450
  • 5 April - 14 June 2025
06 Days
14 Hours
10 Minutes
34 Seconds

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RISC-V Roadshow on SHAKTI Ideology

VSDSquadron was launched by Prof. V. Kamakoti, Director of IIT Madras

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VSD Launches VSDSquadron In Collaboration With IIT Madras & DIR-V

Unleashing VLSI

Job Roles, Convergence With Embedded Systems, and Startups

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VSD showcased at Semicon India 2023

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Karnataka VLSI roadshow at Sahyadri College, Mangalore

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