Anand Rajgopalan Completed bachelor’s in Electrnics & Telecomm Enginnering from Mumbai University. Microelectronics was my elective subject in one of the semesters. Design & Synthesis of Real time clock in Altera CPLD board . Presently I have took training from VLSI Guru, Bangalore in Functional Verilog , did some projects based on AXI protocol and memory verification
