Hello
While trying to build a clock tree which is power aware, let’s go back a step ahead and look, what are the top observations for a clock network, and below image covers the same.
Assuming a slew of ’40ps’ for the first buffer and capacitance of 60fF on node ‘A’, the delay of the first buffer can be easily evaluated using below NLDM table and it comes out to be x9′
And similarly, for the second level of buffering, the delay of the buffers ‘2’ and ‘3’ comes out to be y15 assuming a slew of ’60ps’ and capacitance of ’50fF’ at node ‘B’ and ‘C’ (as I have built a close-to-perfect clock tree:))
This in turn results to ‘zero’ skew at clock endpoints
A detailed explanation on the above is present in my Clock Tree Synthesis Course on Udemy
Now, that’s important thing we jumped into. While we are trying to modify the above clock tree to be power aware, we need to make sure the above observations are retained. That’s where the challenge lies.
Let’s describe the problem statement here:
In below case where 2 flops are active under certain values of ‘EN’ and the other 2 flops are active all the time, we can use an AND gate to get that functionality
But look what happens, just as we plug the AND gate in the circuit:
1) the output capacitance for buf ‘1’ varies — No problem
2) the output capacitance at node ‘B’ and node ‘C’ remains same — Excellent
3) the delay of level 2 gates (buffer for top path and AND gate for bottom path) varies — Big problem, as this will disturb the skew, which we had designed to be ‘zero’
Now that we are clear with the problem statement, it would be easy to rack our brains towards the solution for this, which takes us back to our first post on this topic.
“If I had an hour to save the world I would spend 59 minutes defining the problem and one minute finding solutions” And I find in most organizations people are running around spending sixty minutes finding solutions to problems that don’t matter.“ – Albert Einstein
So, looks like, we are on the right track :). Stay tuned to solve this one
–Kunal
