RISC-V based MYTH + Design Project

Microprocessor for You in Thirty Hours

The “RISC-V based MYTH (Microprocessor for You in Thirty Hours)” workshop provides a structured introduction to RISC-V architecture, covering software-to-hardware concepts through hands-on labs. Participants begin with C programming, GCC compilation, and Spike simulation before progressing to number systems and assembly programming. The workshop delves into combinational and sequential logic, pipeline implementation, and microarchitecture of a single-cycle RISC-V CPU. Labs include instruction decoding, register file operations, ALU implementation, and control flow hazards. The final stages focus on load-store instructions, memory management, and CPU testbench development, offering comprehensive learning experience in microprocessor design and verification.

Overview

The “RISC-V based MYTH (Microprocessor for You in Thirty Hours)” workshop introduces participants to RISC-V architecture, guiding them from software concepts to hardware implementation. It begins with C programming, where learners write and compile simple programs using the RISC-V GCC toolchain. They explore disassembly, simulation with Spike, and debugging techniques. The workshop then covers number systems, explaining signed and unsigned 64-bit representations, crucial for understanding processor arithmetic. These foundational concepts prepare participants for low-level programming and hardware interactions.

Next, the workshop dives into Application Binary Interface (ABI), memory allocation, and assembly-level instruction handling. Participants learn about the 32 general-purpose registers in RISC-V and implement basic operations like load, store, and arithmetic instructions. Function calls and stack management introduce execution flow control. Learners then explore combinational and sequential logic using Makerchip, designing logic gates, multiplexers, and arithmetic circuits. These concepts provide a deeper understanding of how software translates into hardware functionality in microprocessor design.

The workshop then shifts to processor pipeline implementation and microarchitecture. Participants design a single-cycle RISC-V CPU, implementing instruction fetch, decode, and execution stages. Through hands-on labs, they optimize instruction flow, address pipeline hazards, and implement branching mechanisms. Error detection and correction techniques are introduced, ensuring accurate computation. Testing and debugging strategies help participants validate their processor designs, preparing them for real-world challenges in microprocessor development.

In the final phase, learners explore advanced microarchitectural optimizations, including control flow hazards, instruction dependencies, and memory management techniques. They refine instruction execution paths, optimize ALU operations, and implement load-store mechanisms. By the end, participants gain a strong foundation in RISC-V design, having built and optimized their own processor core. This hands-on experience prepares them for careers in semiconductor design, embedded systems, and computer architecture.

Project : Participants may choose one of the following projects to the design:

  1. Branch Predictor Implementation:Implement a branch predictor.
    Options include:
    • A simple two-bit branch predictor
    • A two-level branch predictor
    • A variant of the TAGE predictor for those who want to push their boundaries
  2. Custom RISC-V Instruction: Leverage the RISC-V ISA’s flexibility to add custom instructions.
    Define and implement an instruction not covered by any existing extensions.
  3. GEMM/Convolution
    • Write a C program for GEMM (General Matrix Multiply) or convolution.
    • Compile the program to assembly using the standard RISC-V toolchain or Compiler Explorer.
    • Use the generated assembly as a test program for your RVMYTH CPU.
    • Compare the latency between the pipelined and non-pipelined versions, and report the number of branch misses along with the penalty cycles.

This workshop is your gateway to:

  • Understanding the transition from software to hardware through RISC-V architecture.
  • Learning assembly programming, GCC compilation, and debugging with Spike simulation.
  • Exploring number systems, memory allocation, and RISC-V instruction set implementation.
  • Building logic circuits using combinational and sequential logic concepts.
  • Designing a single-cycle RISC-V CPU, implementing instruction fetch, decode, and execution.
  • Addressing pipeline hazards and optimizing processor performance.
  • Developing load-store mechanisms and memory management techniques.
  • Creating and testing a complete RISC-V core, preparing for real-world hardware design.

Seize this hands-on learning opportunity to master microprocessor design!

5 Compelling Reasons to Join the Workshop

  • 1 Comprehensive Learning Path
  • 1.1 Covers both software and hardware aspects of RISC-V
  • 1.2 Learn assembly programming, debugging, and simulation techniques.
  • 1.3 Build a functional RISC-V processor from scratch.
  • 2 Hands-on Experience
  • 2.1 Work on real-world labs with step-by-step guidance.
  • 2.2 Implement register files, ALUs, and instruction decoders.
  • 2.3 Simulate and test your own processor design.
  • 3 Industry-Relevant Skills
  • 3.1 Gain expertise in microprocessor architecture and design.
  • 3.2 Learn pipeline optimization and memory management.
  • 3.3 Enhance debugging and performance tuning skills.
  • 4 Engagement with Open-Source Tools
  • 4.1 Work with Makerchip, Spike, and RISC-V GCC.
  • 4.2 Develop expertise in combinational and sequential logic.
  • 4.3 Contribute to open-source processor development.
  • 5 Career & Research Opportunities
  • 5.1 Prepares for roles in VLSI, embedded systems, and RISC-V startups.
  • 5.2 Builds a strong foundation for higher studies and research.
  • 5.3 Gain an edge in technical interviews and hardware competitions.

Curriculum

  • Master RISC-V & GNU Toolchain – Learn the fundamentals of RISC-V ISA, compiling, debugging, and executing programs.
  • Explore ABI & Verification – Understand function calls, memory management, and essential verification techniques for hardware design.
  • Design Digital Logic with TL-Verilog & Makerchip – Build and simulate logic circuits interactively using industry-leading tools.
  • Construct a Basic RISC-V CPU – Implement a single-cycle microarchitecture, covering registers, ALUs, and instruction execution.
  • Advance to a Pipelined RISC-V CPU – Optimize CPU performance by handling hazards, control flow, and memory operations.
  • Join this workshop and transform your passion for microprocessors into real-world skills!

Workshop Daywise Content

Module 1

Introduction to RISC-V ISA and GNU compiler toolchain

  • Introduction to RISC-V basic keywords
  • Labwork for RISC-V software toolchain
  • Integer number representation
  • Signed and unsigned arithmetic operations

Module 2

Introduction to ABI and basic verification flow

  • Application Binary interface (ABI)
  • Lab work using ABI function calls
  • Basic verification flow using iverilog

Module 3

Digital Logic with TL-Verilog and Makerchip

  • Combinational logic in TL-Verilog using Makerchip
  • Sequential and pipelined logic
  • Validity
  • Hierarchy

Module 4

Basic RISC-V CPU micro-architecture

  • Microarchitecture and testbench for a simple RISC-V CPU
  • Fetch, decode, and execute logic
  • RISC-V control logic

Module 5

Complete Pipelined RISC-V CPU micro-architecture/store

  • Pipelining the CPU
  • Load and store instructions and memory
  • Completing the RISC-V CPU
  • Wrap-up and future opportunities

Many people have been asking VSD for a workshop on how to do RTL coding – Well, there you go.

Tools

  • GNU Toolchain (GCC, GDB, Binutils) – Compile, debug, and analyze RISC-V assembly and C programs.
  • Spike RISC-V Simulator – Simulate and debug RISC-V programs in a virtual environment.
  • Makerchip & TL-Verilog – Design and simulate digital circuits interactively in the cloud.
  • Verilator – Perform high-speed simulation of hardware designs for verification.
  • GTKWave – Visualize and debug waveform outputs from simulations.
  • RISC-V RTL & Custom CPU Design Frameworks – Implement and test a basic and pipelined RISC-V processor.

Lab Exercises

  • RISC-V assembly programming – Write and debug low-level code.
  • Instruction execution and simulation – Use Spike to analyze CPU behavior.
  • Pipeline implementation and hazard handling – Optimize CPU performance.
  • ALU and memory operations – Develop arithmetic logic and load/store instructions.
  • Microarchitecture validation – Test and verify a functional RISC-V core.

Projects Covered in the Workshop

  • Design and Simulation of a RISC-V ALU – Implement and test arithmetic and logic operations.
  • Building a Pipelined RISC-V Processor – Develop a multi-stage pipeline with hazard handling.
  • Creating a Simple RISC-V Emulator – Execute and debug RISC-V instructions using Spike.

Delivery Mode

  • Virtual Coach platform with expert instructor guidance
  • Cloud-based dedicated Virtual Machine to perform Design labs
  • Intelligent Assessment Technology (IAT) and Project allocation
  • 24 hours Lab access for 5 days and Instructor assistance on demand
  • Simulate basic C program using RISC-V ISA simulator, debug using Spike - all on VSD-IAT platform
  • Design own RISC-V core using TL-Verilog and verify using verilator - all on Makerchip IDE

Instructor Profile

Meet Your Guides to the World of VLSI Design

Steve Hoover, founder of Redwood EDA, Steve is fostering an open-source silicon ecosystem through numerous technologies including the WARP-V CPU core generator with support for RISC-V. His main focus is design methodology and tools enabled by Transaction-Level Verilog (TL-Verilog), available to all at makerchip.com. He is also the lead developer of the 1st CLaaS open-source framework for cloud FPGAs. Steve holds a BS in electrical engineering summa cum laude from Rensselaer Polytechnic Institute and an MS in computer science from the University of Illinois. He has designed numerous components for high-performance server CPUs and network architectures for DEC, Compaq, and Intel.

FAQ

Can I participate on my schedule in my timezone?

Yes, also you will be provided roughly 24x7 live support from mentors in various time zones over the duration of the workshop. We use Slack for live chat support and do also take up daily sync-up and one-to-one calls, as necessary.

Can experienced system designers join for refreshing concepts?

We welcome interested participants from all stages of their career. Even if you have learned logic design and CPU microarchitecture in the past, this course offers a modern perspective. TL-Verilog is a new and emerging standard and is useful for industry and academia alike. Get involved in revolutionizing your design/teaching/learning process!

I’m new to digital logic. Will I be able to complete the course?

This course teaches the basics of digital logic in the context of a modern design approach. So newcomers will learn something just as well as experienced designers. We have received positive feedback from learners ranging from 12 years of age to industry veterans, though we suggest this course for college age and above for folks on a technical path.

Can I access content after Workshop is finished ?

The main tool used in the workshop is the Makerchip.com online IDE, which is public and always open for development of open-source designs. You will also be given lifetime access to the slides and lab files after the workshop.

Do I need to install any software or tools to do labs?

No. Labs will be done on VSD-IAT cloud platform and Makerchip.com online IDE. You will be given access in your browser to a Linux Terminal, which has all necessary tools installed. Post workshop, we will provide scripts and templates to install or use the tools on your personal systems.

How is TL-Verilog different from Verilog?

TL-Verilog (Transaction-Level Verilog) is a new and emerging standard supporting “timing abstract” digital design, without which this course would not be possible. In addition to its powerful modeling constructs, it also eliminates legacy complexities of Verilog such as regs and wires, generate blocks, blocking vs. non blocking etc. It provides clean semantics that are easy to learn whether you already know Verilog or not. It integrates with existing commercial and open-source EDA tools by generating synthesizable (System)Verilog.
Learn more at https://www.redwoodeda.com/tl-verilog

Hardware Design Program
Refund Policy

If you are not able to join workshop, last date to apply for refund in 5th Feb 2025, 11:59 PM IST

T & C

Registration Fees

₹1800
$70 $25
  • 5 March - 14 March 2025
  • Duration: 10 Days
  • Format: Cloud based Virtual Training Workshop

Burn RISC-V core on VSDSquadronFPGA Mini

RISC-V based MYTH = ₹1800

+

VSDSquadronFPGA Mini = ₹2599

Offer Price

$62 $55
₹4399 ₹3799

About VSD

VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.

Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.

At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.

We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.

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