Master RTL Design & Synthesis for VLSI Interview Labs

Crack for Level 1 Digital Design Technical Rounds through labs

(Duration - 10 Days)

Overview

The semiconductor industry is undergoing a major shift towards open-source toolchains and PDKs like SKY130 for chip prototyping and tapeout.

This workshop empowers you to master Register Transfer Level (RTL) design, simulation, and synthesis using industry-aligned open-source tools.

Compelling reasons to join this workshop

Curriculum

Modulewise Content

Course Highlights

Skills You Will Gain

Tools You Will Use

Delivery Mode

Lab Exercises

Possible Projects List

Pre-requisites

Eligibility

Instructor Profile


Kunal Ghosh, the visionary co-founder of VLSI System Design (VSD) Corp. Pvt. Ltd., stands at the forefront of online open-source EDA and hardware design education, particularly in the realm of RISC-V.

With a portfolio of 50 top-tier VLSI online courses, Kunal has enriched the learning journey of over 90,000 students across 153 countries. His expertise extends beyond training; he’s actively involved in pioneering open-source projects and design collaborations with esteemed institutions like IIT Madras, IIT Bombay, IIT Guwahati and IIT Hyderabad.

His current focus is on crafting high-quality open-source Analog/Digital IPs, a groundbreaking endeavor in open-source hardware design. Kunal’s rich industry experience includes roles at Qualcomm and Cadence, specializing in SoC design. He holds a master’s degree from IIT Bombay, where he specialized in VLSI & Nano-electronics, with a focus on sub-100nm Electron Beam Lithography Optimization techniques.

Frequently Asked Questions (FAQs)

Do I need to know Verilog before joining?

No. This workshop begins from basic concepts and builds up to synthesis.

Can I run labs without a SKY130 PDK installation?

Yes. You will use pre-configured cells and open-source tools that work in local or cloud environments.

Will I get experience useful for real tapeouts?

Absolutely. You’ll use industry-accepted synthesis tools (Yosys) and SKY130 libraries which are used in real chip tapeouts.

Will I receive a certificate?

Yes. Participants who complete labs and attend all sessions will receive a completion certificate.

What if I miss a session?

All sessions are recorded and available during the 10-days duration of the program

VSD Participants Profile

Registration Fees

Workshop intends to teach the verilog coding guidelines that results in predictable logic in Silicon

Next Cohort will start in

08 Days
07 Hours
43 Minutes
07 Seconds
Master RTL Design & Synthesis = ₹1800

+

VSDSquadronFPGA Mini = ₹2599

Offer Price

About VSD

VSD, standing as a trailblazing Semiconductor EdTech company and a community-based Technology Aggregator, is revolutionizing the landscape of VLSI Design. With the belief that “Creativity is just connecting things”, VSD has mastered the art of linking the right resources with the community. This unique approach has sparked a significant transformation in the VLSI Design process.

Over the past decade, VSD has made remarkable strides in the open-source semiconductor domain. Our journey includes the development of comprehensive training content, empowering students to design silicon-grade IP/SoC. Notably, we’ve successfully guided these projects through the tapeout cycle via the Google open shuttle program. This achievement is a testament to our commitment to hands-on, practical education.

At VSD, our role extends beyond traditional education. While we didn’t invent EDA tools or design flows, we’ve made them accessible to a wider community. Our mentorship has been instrumental in the development of over 50+ Analog/Digital IPs and solutions. Impressively, 20+ of these have successfully transitioned from concept to Silicon – a clear indicator of our effective approach and the high quality of work produced under our guidance.

We pride ourselves on fostering a community-based revolution in the Semiconductor Industry. By democratizing access to advanced tools and knowledge, VSD is not just educating individuals; we are building a community of innovators poised to lead the next wave of advancements in the semiconductor sector. With VSD, the future of VLSI Design is not just being written; it’s being rewritten by a passionate and empowered community.

Media Coverage

VSD Team interview taken by DD News at SEMICON India 2024

RISC-V Roadshow on SHAKTI Ideology

VSDSquadron was launched by Prof. V. Kamakoti, Director of IIT Madras

Innovation & Education Unite

VSD Launches VSDSquadron In Collaboration With IIT Madras & DIR-V

Unleashing VLSI

Job Roles, Convergence With Embedded Systems, and Startups

Semicon India Future Skills by IESA

VSD showcased at Semicon India 2023

Puthiya Thalaimurai

VSDSquadron Educational board on Tamil News channel

NIT Jamshedpur

5 Day Workshop on VLSI Design Flow using RISCV and EDA Tools

Sahyadri College

Karnataka VLSI roadshow at Sahyadri College, Mangalore