Selective Non-Default Rules Based Clock Tree Synthesis using open-source EDA
Hey There – Think about it…!! Problem Statement – For hierarchical designs ~500k instance count, participants are expected to develop code which will modify existing […]
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Are you analyzing noise? Then meet me, I am CCC
A channel connected component (CCC). For some reasons, I feel my friends in CAD company or my leads are not able to introduce me very […]
Clk-to-q delay, library setup and hold time – Part 2
Hello, This is in continuation to the previous post, where I explained about transistor level implementation of negative and positive latch. In this post, I […]
Clk-to-q delay, library setup and hold time – Part 1
Hello, I have been receiving multiple queries on what is clk-to-q delay, how’s it different from library setup time and library hold time, etc. I […]
