Skywater130 Spec to GDS workshop details
You might have seen the above image in one form or another, in different our blogs or VSD websites. Every trapezoid in above image is […]
Tag Archives: SoC physical design
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Chennai, we are coming to you for next RISC-V workshop…
So glad and happy to let you know that we will be presenting in RISC-V workshop at IIT Madras, India, on July 19, 2018 at 2pm (organized by RISC-V foundation), and topic is something which we have mastered in last 7 years – its about a survey of E31 RISC-V core floorplan and its impact on power, performance and area.
Symposium III – Floorplanning of digital IC’s for best area
This blog is regarding abstract submission for VSDOpen2018, which is the first online conference in VLSI, that covers all aspects of semiconductor technology with prime focus to build SoC using RISC-V CPU by illustrating exciting ways using (only) opensource EDA tools.
