sta – Page 2 – VLSI System Design

Memory, tristate and library characterization – how are all connected?

Hi I am happy to say, they really are connected….Let’s figure out how? If you see a classic application of tri-state buffer, it’s the memory […]

Timing libraries – This is where body and soul meets…!!

Get geared up for my next “to be” launched course on CCS timing libraries – Constructs and characterization. Let me be a bit frank here […]

Jitter analysis using eye diagram – Part 1

Hello For those who have been in sync with my course on Static timing analysis, will already know this topic very well. For those who […]

CMOS VTC – Believe it or not – You use it ‘daily’ – Part 4

Hello Long time … since my last post …. Reason : Hopefully, I have given enough time for you to get hold on my previous […]

CMOS VTC – Believe it or not – You use it ‘daily’ – Part 3

Hello If you have read through my previous posts on the above topic, things have seriously become interesting over here. I mean, isn’t that exciting, […]

CMOS VTC – Believe it or not – You use it ‘daily’ – Part 2

Hello I will derive the CMOS VTC in few steps, and below is the first one. We did derive the below equations sometime back, and […]

On-Chip Variation (OCV) – Part 4

Hello And, finally, we have a video on what we posted on this topic. Below is the snippet of the same. Full video can be […]

On-Chip Variation (OCV) – Part 3

Hello, The below image models “low-to-high waveform condition” at input of CMOS inverter, in terms of resistances and capacitance. So, overall, its the RC time […]