About me….
Never really found a chance to properly introduce myself and my background to all of you. So here it is… My name is Kunal Ghosh […]
Tag Archives: Static Timing Analysis
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VLSI interviews or deep concepts – This one covers it all…
Its a glimpse of physical design flow, static timing analysis, static circuit simulation, dynamic circuit simulations, leakage & switching power concepts, crosstalk glitch & delta delay concepts and basic delay of a cell.
“20ps < clock_tran < 60ps”, ever wondered what’s the real reason?
I am sure you must have…. This blog will just walk you through the reasons using cool images from my latest course on “Static Timing […]
Clock gating analysis – why, what, how?
Hello Now let me first be very clear – This blog is for freshers in static timing analysis domain. This topic had been very confusing […]
The curious case of ‘interface analysis’!!
Hello This is an important part of static timing analysis, Below is the link: https://www.udemy.com/vlsi-academy-sta-checks-2 I would love to talk about it a lot in […]
Hey is your laptop ready to design a chip??
Hello Or atleast analyze full chip timing? No…..Then get it ready soon… We will soon be launching course on static timing analysis – part 2 […]
Generated clock & master clock.. Let’s make it simple!! – Part 3
Hello So now that you get the point of generated clocks in previous Part 1 and Part 2 of this post, now let’s conclude this […]
Generated clock & master clock.. Let’s make it simple – Part 2
hello Based on the responses of previous post of Generated clock & master clock … Let’s make it simple!! – Part 1, I am very […]
Generated clock & master clock.. Let’s make it simple!! – Part 1
Hello I get this one occasionally … not particularly about the concept, but about the ways we can create a generated clock definition. Too many […]
Jitter analysis using eye diagram – Part 1
Hello For those who have been in sync with my course on Static timing analysis, will already know this topic very well. For those who […]
