Tools related – Page 2 – VLSI System Design

Report QOR (Quality Of Results)

Above images plays a huge role in closing on gaps between a tool user (customers who use the tool) and product engineer/manager (one who manages the tool TCL interface)

read_sdc – clock constraints

read_sdc is been considered as a very critical command in EDA world, as this is the command which defines your specifications, and if not written and interpreted correctly, can lead a huge delay in tapeout cycle.

set_multi_cpu_usage -localCpu 8

Looks like a very popular EDA command, isn’t it? Yes, it is. Well, this command actually is just an interface for users. At the back-end, […]

ORCONF 2017 – An Olympic Like Platform for Open-source

And glad, we are a part of it this time…. If you know names like Usain Bolt or Michael Fred Phelps, you would have, probably […]

VLSI interviews or deep concepts – This one covers it all…

Its a glimpse of physical design flow, static timing analysis, static circuit simulation, dynamic circuit simulations, leakage & switching power concepts, crosstalk glitch & delta delay concepts and basic delay of a cell.

Hey, its time you take charge of your design!!

….And this is something which I can show you using the newly launched open-source EDA tool “eSim (FOSSEE IITB Project)”. Let’s assume for a moment, […]

eSim Tool – From 2015 Vision to 2017 Reality

If you had been following me on linkedin or Udemy, you would have had received an announcement from me in the year 2015, where I […]

vlsisystemdesign.com – re-created, revamped and re-published – its cooler now!!

vlsisystemdesign.com – The website which started with basic hand-drawn diagrams and blogs is now being re-created, revamped and re-published. This time, it more cooler and […]