Power aware clock tree synthesis – Part 4
Hello We were looking for a solution for below scenario, and you will be amazed to see, how an ‘Universal Gate’ solves the below problem […]
Tag Archives: ‘zero’ skew at clock endpoints
Continue reading
Power aware clock tree synthesis – Part 3
Hello And here’s the solution to the problem posted in my previous article. ‘AND gate itself’. If you observe carefully, you tie one of the […]
Power aware clock tree synthesis – Part 2
Hello While trying to build a clock tree which is power aware, let’s go back a step ahead and look, what are the top observations […]
