VLSI System Design

Kunal P. Ghosh, M.Tech (VLSI & Nanoelectronics), IIT Bombay
Vijayamanohar. N, M.Tech (Electronics Design and Technology), IISc Bangalore
 
INDUSTRIAL PHYSICAL DESIGN FLOW
 
 
 
 
 
 
 
 
 
 
 
NEW TOPIC
 
 
 
UPCOMING TOPICS
  
 
 
 
 

 

 
KUNAL P GHOSH
 
I, Kunal P Ghosh, Physical Design Engineer at Qualcomm in Bangalore India, did Masters from IIT- Mumbai in Microelectronics & VLSI in 2010, as Research Assistant.

My current course of work affords me a large amount of exposure to, and experience in a variety of VLSI design tools, such as Magma Talus, Cadence Encounter, Synopsys Primetime, etc., as do my own personal interests most of which are centred around Physical Design.

Things I've worked on as a part of MTech course:
1) Characterization of RTL (in terms of power, delay & area) generated by A Hardware Intermediate Representation Flow
2) “Sub-100nm optimization using Raith 150Two Electron Beam Lithography System”
 
I have worked on objective-based projects like Timing Closure of Modem Testchips, power-planning, Crosstalk Analysis and Engineering Change Order (ECO). 
 
My work involves lot of scripting activities to quickly automate routine computing tasks using shell, tcl, perl, etc., which helps me to increase my productivity.
 
Any Queries, you can mail on my personal mail id
 
N.VIJAYAMANOHAR IYER
 
Vijayamanohar. N did his B.E. in Electronics and Instrumentation Engineering from University of Madras, in 2004. After B.E., he worked in Power Plant Commissioning and Operations for 4 years.
 
Later, he pursued his MTech in Electronics Design and Technology from CEDT, IISc Bangalore. He has done many projects as a part of his MTech course as well as part of hobby. These include the implementation of digital systems in FPGA (Xylinx Spartan and Virtex Devices), ARM based Embedded System Projects.
 
Presently, he's working for Qualcomm as an Engineer in the Front-End Design Team.
 
Vijayamanohar has given a valuable contribution in the forum.
 
ANAGHA K GHOSH
 
Anagha K Ghosh, has done her B.E. in Electrical Engineering and Diploma in Electrical and Power System from V.J.T.I  Mumbai.
 
She was Power Engineer in Tata Power Hydro Division Mumbai for 2 Years and Project Manager in Tata Power SED Bangalore.
 
Anagha is currently pursuing her Master's in Business Law from National law School India University ( NLSIU) Bangalore.
 
She has given a technical support to the website, also the concept and designs of the website are  done by her. And done the proof reading of all the drawings and the topics explained in website.
 
 
WELCOME TO OUR WEBSITE!!!
 
In the last few years, I found a whole new respect for Physical Design because of the kind of projects I was involved into and I have gained professional knowledge of the Physical Design Flow.
 
Over the period of time, I realised that many engineers in VLSI field know 'HOW' to do certain things, but very few know 'WHAT' they are doing and 'WHY' are they doing it.
 
"Vision without execution is hallucination." - Thomas A. Edison
 
To enjoy the work, it’s not enough just to expertise the VLSI design tools. The key to enjoy work is to use the right concepts, at the right time, with the right purpose, for the right project.
 
Learning is not instinctive. Everyone who teaches you has at some time had to go through the process of learning. 
 
Hence, we have tried to squeeze in some concepts related to chip design flow into this website using very simple diagrams.  
 
Hope you ENJOY while you WORK!!!!
 

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